SpinalHDL/VexRiscv

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

3232 stars · 512 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

VexRiscv is a parameterizable 32-bit RISC-V CPU core written in SpinalHDL that generates Verilog for FPGA deployment. It supports RV32I[M][A][F[D]][C] instruction sets, 2-5+ stage pipelines, and includes a plugin system for adding custom instructions, CSRs, and peripherals.

Use cases

• implement a RISC-V softcore CPU on an FPGA
• build a SoC with a customizable RISC-V processor
• run Linux on a small FPGA softcore
• add custom instructions to a RISC-V CPU
• simulate and debug a RISC-V CPU with GDB and Verilator
• learn pipelined CPU design and computer architecture
• generate Verilog for a pipelined RISC-V core from Scala code

When to choose

• you need an FPGA-friendly RISC-V CPU without vendor-specific IP blocks
• you want a highly configurable pipeline (stages, caches, MMU, FPU, branch prediction)
• you need to add custom instructions or CSRs via a plugin architecture
• you want to run Linux or bare-metal software on a softcore with JTAG debugging

When to avoid

• you need an ASIC-taped-out or formally verified processor
• you require maximum performance rather than FPGA area/frequency efficiency
• you are not comfortable working with SpinalHDL/Scala or generated Verilog
• you need a hard CPU core or out-of-order superscalar design

Facets

library · maturity active

embedded simulation compiler hardware embedded-systems cross-platform risc-v softcore-cpu spinalhdl fpga soc verilog-generation pipelined-cpu open-source-hardware computer-architecture

Member repositories

For agents

markdown · JSON · MCP: product_card(name="SpinalHDL/VexRiscv")