# SpinalHDL/VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Repository: https://github.com/SpinalHDL/VexRiscv
Canonical: https://ross.abutalabs.com/products/vexriscv
Language: Assembly
License: MIT
License Family: permissive
Topics: riscv, soc, cpu, spinalhdl, vhdl, verilog, fpga, softcore
Last push: 2026-02-11T09:06:28+00:00

## Health v2 (maintenance only)
Score: 62/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 67, release rhythm 35, longevity 100
- inputs: {"age_days": 3465, "days_push": 203, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3232, forks 512 (observed 2026-08-28T04:07:50.169498+00:00)

## What it is
VexRiscv is a parameterizable 32-bit RISC-V CPU core written in SpinalHDL that generates Verilog for FPGA deployment. It supports RV32I[M][A][F[D]][C] instruction sets, 2-5+ stage pipelines, and includes a plugin system for adding custom instructions, CSRs, and peripherals.

## Use cases
- implement a RISC-V softcore CPU on an FPGA
- build a SoC with a customizable RISC-V processor
- run Linux on a small FPGA softcore
- add custom instructions to a RISC-V CPU
- simulate and debug a RISC-V CPU with GDB and Verilator
- learn pipelined CPU design and computer architecture
- generate Verilog for a pipelined RISC-V core from Scala code

## When to choose
- you need an FPGA-friendly RISC-V CPU without vendor-specific IP blocks
- you want a highly configurable pipeline (stages, caches, MMU, FPU, branch prediction)
- you need to add custom instructions or CSRs via a plugin architecture
- you want to run Linux or bare-metal software on a softcore with JTAG debugging

## When to avoid
- you need an ASIC-taped-out or formally verified processor
- you require maximum performance rather than FPGA area/frequency efficiency
- you are not comfortable working with SpinalHDL/Scala or generated Verilog
- you need a hard CPU core or out-of-order superscalar design

## Facets
- artifact type: library
- maturity: active
- function: embedded, simulation, compiler
- domain: hardware, embedded-systems
- platform: cross-platform
- tags: risc-v, softcore-cpu, spinalhdl, fpga, soc, verilog-generation, pipelined-cpu, open-source-hardware, computer-architecture

## Member repositories
- SpinalHDL/VexRiscv (main) score 62

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:07:50.169498+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T07:24:37.639555+00:00, confidence not recorded.
  - readme: https://github.com/SpinalHDL/VexRiscv (fetched 2026-08-28T04:07:50.169498+00:00, sha fc5c25d7ef29)
- Data as of 2026-08-30T08:39:29.467469+00:00.