alexforencich/verilog-pcie

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

1646 stars · 420 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A collection of Verilog PCI Express components including PCIe-to-AXI/AXI-Lite bridges and a high-performance DMA subsystem for FPGA designs. It supports Xilinx and Intel FPGA families and ships with full cocotb testbenches and example designs for many boards.

Use cases

• implement a PCIe endpoint with DMA on an FPGA
• bridge PCIe BARs to AXI or AXI-Lite in Verilog
• build a custom PCIe accelerator card design
• simulate PCIe TLP traffic with cocotb testbenches
• port the same PCIe core logic across Xilinx and Intel FPGAs
• add MSI interrupt support to an FPGA PCIe design

When to choose

• you need reusable, FPGA-independent PCIe RTL for Xilinx or Intel devices
• you want a proven DMA subsystem with full cocotb verification
• you need example designs for common boards like Alveo or Stratix 10

When to avoid

• you need a soft PCIe PHY rather than using vendor hard IP
• your target FPGA family is not Xilinx 7-series/UltraScale or Intel Stratix 10/Agilex
• you want a higher-level driver or host-side software stack

Facets

library · maturity active

embedded developer-tools testing hardware embedded-systems developer-tools embedded pcie verilog fpga axi dma cocotb xilinx intel

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