# alexforencich/verilog-pcie

Verilog PCI express components

Repository: https://github.com/alexforencich/verilog-pcie
Canonical: https://ross.abutalabs.com/products/verilog-pcie
Language: Verilog
License: MIT
License Family: permissive
Last push: 2024-04-26T17:15:29+00:00

## Health v2 (maintenance only)
Score: 32/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 2794, "days_push": 859, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1646, forks 420 (observed 2026-08-28T04:05:16.309120+00:00)

## What it is
A collection of Verilog PCI Express components including PCIe-to-AXI/AXI-Lite bridges and a high-performance DMA subsystem for FPGA designs. It supports Xilinx and Intel FPGA families and ships with full cocotb testbenches and example designs for many boards.

## Use cases
- implement a PCIe endpoint with DMA on an FPGA
- bridge PCIe BARs to AXI or AXI-Lite in Verilog
- build a custom PCIe accelerator card design
- simulate PCIe TLP traffic with cocotb testbenches
- port the same PCIe core logic across Xilinx and Intel FPGAs
- add MSI interrupt support to an FPGA PCIe design

## When to choose
- you need reusable, FPGA-independent PCIe RTL for Xilinx or Intel devices
- you want a proven DMA subsystem with full cocotb verification
- you need example designs for common boards like Alveo or Stratix 10

## When to avoid
- you need a soft PCIe PHY rather than using vendor hard IP
- your target FPGA family is not Xilinx 7-series/UltraScale or Intel Stratix 10/Agilex
- you want a higher-level driver or host-side software stack

## Facets
- artifact type: library
- maturity: active
- function: embedded, developer-tools, testing
- domain: hardware, embedded-systems, developer-tools
- platform: embedded
- tags: pcie, verilog, fpga, axi, dma, cocotb, xilinx, intel

## Member repositories
- alexforencich/verilog-pcie (main) score 32

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:16.309120+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:45:22.434356+00:00, confidence not recorded.
  - readme: https://github.com/alexforencich/verilog-pcie (fetched 2026-08-28T04:05:16.309120+00:00, sha 205e6d824ff4)
- Data as of 2026-08-30T08:39:29.467469+00:00.