alexforencich/verilog-ethernet

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

3074 stars · 852 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A collection of Verilog Ethernet components for FPGA implementation, covering gigabit, 10G, and 25G packet processing with MAC, PCS/PMA PHY, IP/UDP/ARP stack modules, and PTP time synchronization components. It includes full cocotb testbenches and example designs for many FPGA development boards.

Use cases

• implement a UDP/IP stack on an FPGA
• build a 10G Ethernet MAC in Verilog
• add precise PTP time synchronization to FPGA designs
• process Ethernet frames with 8-bit or 64-bit datapaths
• simulate Ethernet components with cocotb testbenches
• create a UDP echo server on an FPGA dev board

When to choose

• you need reusable Verilog modules for Ethernet, IP, UDP, ARP, or PTP on FPGAs
• you want tested components with cocotb testbenches and board-level example designs
• you need gigabit to 25G Ethernet support with MIT licensing

When to avoid

• you are starting a new project - the repo is deprecated in favor of fpganinja/taxi
• you need commercial support or ongoing maintenance
• you need Ethernet components in VHDL or for non-FPGA targets

Facets

library · maturity maintenance

networking developer-tools testing hardware embedded-systems networking developer-tools embedded fpga ethernet verilog udp ptp mac phy cocotb hardware-design deprecated

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