# alexforencich/verilog-ethernet

Verilog Ethernet components for FPGA implementation

Repository: https://github.com/alexforencich/verilog-ethernet
Canonical: https://ross.abutalabs.com/products/verilog-ethernet
Language: Verilog
License: MIT
License Family: permissive
Last push: 2025-02-27T23:50:33+00:00

## Health v2 (maintenance only)
Score: 36/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 8, release rhythm 35, longevity 100
- inputs: {"age_days": 4305, "days_push": 552, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3074, forks 852 (observed 2026-08-28T04:07:41.692577+00:00)

## What it is
A collection of Verilog Ethernet components for FPGA implementation, covering gigabit, 10G, and 25G packet processing with MAC, PCS/PMA PHY, IP/UDP/ARP stack modules, and PTP time synchronization components. It includes full cocotb testbenches and example designs for many FPGA development boards.

## Use cases
- implement a UDP/IP stack on an FPGA
- build a 10G Ethernet MAC in Verilog
- add precise PTP time synchronization to FPGA designs
- process Ethernet frames with 8-bit or 64-bit datapaths
- simulate Ethernet components with cocotb testbenches
- create a UDP echo server on an FPGA dev board

## When to choose
- you need reusable Verilog modules for Ethernet, IP, UDP, ARP, or PTP on FPGAs
- you want tested components with cocotb testbenches and board-level example designs
- you need gigabit to 25G Ethernet support with MIT licensing

## When to avoid
- you are starting a new project - the repo is deprecated in favor of fpganinja/taxi
- you need commercial support or ongoing maintenance
- you need Ethernet components in VHDL or for non-FPGA targets

## Facets
- artifact type: library
- maturity: maintenance
- function: networking, developer-tools, testing
- domain: hardware, embedded-systems, networking, developer-tools
- platform: embedded
- tags: fpga, ethernet, verilog, udp, ptp, mac, phy, cocotb, hardware-design, deprecated

## Member repositories
- alexforencich/verilog-ethernet (main) score 36

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:07:41.692577+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T07:27:56.250019+00:00, confidence not recorded.
  - readme: https://github.com/alexforencich/verilog-ethernet (fetched 2026-08-28T04:07:41.692577+00:00, sha 9fa758955e99)
- Data as of 2026-08-30T08:39:29.467469+00:00.