alexforencich/verilog-axi

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

2120 stars · 538 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A collection of parametrizable Verilog components implementing AXI4 and AXI4-Lite bus functionality for FPGA designs, including adapters, crossbars, and DMA engines. It includes full cocotb testbenches, but the repository is deprecated in favor of the fpganinja/taxi project.

Use cases

• implement AXI4 interconnect in an FPGA design
• convert AXI to AXI4-Lite in Verilog
• add a DMA engine to my FPGA project
• find parametrizable AXI crossbar RTL modules
• verify AXI components with cocotb testbenches
• adapt AXI bus widths in hardware design

When to choose

• you need proven, tested AXI4/AXI4-Lite RTL components for an FPGA project
• you want fully parametrizable interface widths and cocotb-based verification
• you are maintaining an existing design already built on these modules

When to avoid

• you are starting a new project - use the successor fpganinja/taxi instead
• you need commercial support or ongoing bug fixes
• you need AXI components for non-FPGA or non-Verilog workflows

Facets

library · maturity maintenance

developer-tools embedded-systems hardware developer-tools embedded verilog fpga axi axi4 axi-lite cocotb rtl hardware-design interconnect deprecated

Member repositories

For agents

markdown · JSON · MCP: product_card(name="alexforencich/verilog-axi")