# alexforencich/verilog-axi

Verilog AXI components for FPGA implementation

Repository: https://github.com/alexforencich/verilog-axi
Canonical: https://ross.abutalabs.com/products/verilog-axi
Language: Verilog
License: MIT
License Family: permissive
Last push: 2025-02-27T23:57:56+00:00

## Health v2 (maintenance only)
Score: 36/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 8, release rhythm 35, longevity 100
- inputs: {"age_days": 2957, "days_push": 552, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2120, forks 538 (observed 2026-08-28T04:06:16.481250+00:00)

## What it is
A collection of parametrizable Verilog components implementing AXI4 and AXI4-Lite bus functionality for FPGA designs, including adapters, crossbars, and DMA engines. It includes full cocotb testbenches, but the repository is deprecated in favor of the fpganinja/taxi project.

## Use cases
- implement AXI4 interconnect in an FPGA design
- convert AXI to AXI4-Lite in Verilog
- add a DMA engine to my FPGA project
- find parametrizable AXI crossbar RTL modules
- verify AXI components with cocotb testbenches
- adapt AXI bus widths in hardware design

## When to choose
- you need proven, tested AXI4/AXI4-Lite RTL components for an FPGA project
- you want fully parametrizable interface widths and cocotb-based verification
- you are maintaining an existing design already built on these modules

## When to avoid
- you are starting a new project - use the successor fpganinja/taxi instead
- you need commercial support or ongoing bug fixes
- you need AXI components for non-FPGA or non-Verilog workflows

## Facets
- artifact type: library
- maturity: maintenance
- function: developer-tools
- domain: embedded-systems, hardware, developer-tools
- platform: embedded
- tags: verilog, fpga, axi, axi4, axi-lite, cocotb, rtl, hardware-design, interconnect, deprecated

## Member repositories
- alexforencich/verilog-axi (main) score 36

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:16.481250+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T02:52:53.577235+00:00, confidence not recorded.
  - readme: https://github.com/alexforencich/verilog-axi (fetched 2026-08-28T04:06:16.481250+00:00, sha 6056f706e268)
- Data as of 2026-08-30T08:39:29.467469+00:00.