chipsalliance/riscv-dv

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

1350 stars · 394 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

RISCV-DV is a SystemVerilog/UVM-based random instruction sequence generator for verifying RISC-V processor designs. It produces randomized assembly test programs covering RV32/RV64 instruction sets, privileged modes, exceptions, and debug scenarios, with co-simulation against instruction set simulators.

Use cases

• generate random instruction streams to verify a RISC-V CPU core
• stress test RISC-V MMU and page table handling
• co-simulate RTL against spike or other instruction set simulators
• build coverage-driven verification test suites for RV32IMAFDC and RV64IMAFDC
• test trap, interrupt, and exception handling in a RISC-V processor
• generate randomized privileged CSR and debug mode tests

When to choose

• you are verifying a RISC-V processor RTL design and need randomized test programs
• you have access to a commercial SystemVerilog/UVM simulator like VCS, Questa, or Xcelium
• you need coverage-driven instruction generation with ISS co-simulation

When to avoid

• you need a RISC-V simulator or emulator rather than a verification test generator
• you have no SystemVerilog/UVM RTL simulator available
• you want formal verification rather than simulation-based testing

Facets

library · maturity active

testing fuzzing simulation data-generation hardware testing simulation developer-tools python cli risc-v processor-verification instruction-generator systemverilog uvm cosimulation chip-design linux

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