# chipsalliance/riscv-dv

Random instruction generator for RISC-V processor verification

Repository: https://github.com/chipsalliance/riscv-dv
Canonical: https://ross.abutalabs.com/products/riscv-dv
Language: Python
License: Apache-2.0
License Family: permissive
Last push: 2026-04-03T15:17:27+00:00

## Health v2 (maintenance only)
Score: 66/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 75, release rhythm 35, longevity 100
- inputs: {"age_days": 2779, "days_push": 152, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1350, forks 394 (observed 2026-08-28T04:04:28.093738+00:00)

## What it is
RISCV-DV is a SystemVerilog/UVM-based random instruction sequence generator for verifying RISC-V processor designs. It produces randomized assembly test programs covering RV32/RV64 instruction sets, privileged modes, exceptions, and debug scenarios, with co-simulation against instruction set simulators.

## Use cases
- generate random instruction streams to verify a RISC-V CPU core
- stress test RISC-V MMU and page table handling
- co-simulate RTL against spike or other instruction set simulators
- build coverage-driven verification test suites for RV32IMAFDC and RV64IMAFDC
- test trap, interrupt, and exception handling in a RISC-V processor
- generate randomized privileged CSR and debug mode tests

## When to choose
- you are verifying a RISC-V processor RTL design and need randomized test programs
- you have access to a commercial SystemVerilog/UVM simulator like VCS, Questa, or Xcelium
- you need coverage-driven instruction generation with ISS co-simulation

## When to avoid
- you need a RISC-V simulator or emulator rather than a verification test generator
- you have no SystemVerilog/UVM RTL simulator available
- you want formal verification rather than simulation-based testing

## Facets
- artifact type: library
- maturity: active
- function: testing, fuzzing, simulation, data-generation
- domain: hardware, testing, simulation, developer-tools
- platform: python, cli
- tags: risc-v, processor-verification, instruction-generator, systemverilog, uvm, cosimulation, chip-design, linux

## Member repositories
- chipsalliance/riscv-dv (main) score 66

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:28.093738+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:42:16.151733+00:00, confidence not recorded.
  - readme: https://github.com/chipsalliance/riscv-dv (fetched 2026-08-28T04:04:28.093738+00:00, sha 1caacd55b6df)
- Data as of 2026-08-30T08:39:29.467469+00:00.