ultraembedded/riscv

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

1770 stars · 295 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A 32-bit RISC-V CPU core (RV32IMZicsr) written in synthesizable Verilog 2001, accompanied by an instruction set simulator. It supports user/supervisor/machine privilege levels, basic MMU capable of booting Linux, caches, and AXI or tightly-coupled memory interfaces, and has been verified via co-simulation against a C++ ISA model.

Use cases

• implement a RISC-V CPU on an FPGA
• simulate RV32IM instruction execution for verification
• boot Linux on a custom soft CPU core
• integrate a configurable pipelined processor into an SoC design
• verify a RISC-V core against a golden ISA model with co-simulation
• learn how a pipelined RISC-V processor is implemented in Verilog

When to choose

• you need a synthesizable, FPGA-friendly RV32IM core with configurable pipeline and cache options
• you want to boot Linux on a soft core with basic MMU support
• you need a Verilog CPU core verified against a reference ISA simulator
• you want a simple, well-documented RISC-V core for ASIC or FPGA prototyping

When to avoid

• you need higher performance with branch prediction and dual-issue (use biriscv instead)
• you need RV64 or the atomic (A) extension in hardware
• you want a software-only emulator rather than a hardware core
• you need a fully verified, production-grade commercial CPU core

Facets

library · maturity stable

simulation embedded hardware developer-tools cross-platform risc-v cpu-core verilog rv32im instruction-set-simulator asic synthesizable pipeline-processor processors fpga verilator

Member repositories

For agents

markdown · JSON · MCP: product_card(name="ultraembedded/riscv")