# ultraembedded/riscv

RISC-V CPU Core (RV32IM)

Repository: https://github.com/ultraembedded/riscv
Canonical: https://ross.abutalabs.com/products/riscv
Language: Verilog
License: BSD-3-Clause
License Family: permissive
Topics: risc-v, cpu, verilog, fpga, verilator, rv32im, rv32i, riscv-linux, pipeline-processor, asic, verification
Last push: 2021-09-18T17:52:55+00:00

## Health v2 (maintenance only)
Score: 32/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 4385, "days_push": 1810, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1770, forks 295 (observed 2026-08-28T04:05:34.015448+00:00)

## What it is
A 32-bit RISC-V CPU core (RV32IMZicsr) written in synthesizable Verilog 2001, accompanied by an instruction set simulator. It supports user/supervisor/machine privilege levels, basic MMU capable of booting Linux, caches, and AXI or tightly-coupled memory interfaces, and has been verified via co-simulation against a C++ ISA model.

## Use cases
- implement a RISC-V CPU on an FPGA
- simulate RV32IM instruction execution for verification
- boot Linux on a custom soft CPU core
- integrate a configurable pipelined processor into an SoC design
- verify a RISC-V core against a golden ISA model with co-simulation
- learn how a pipelined RISC-V processor is implemented in Verilog

## When to choose
- you need a synthesizable, FPGA-friendly RV32IM core with configurable pipeline and cache options
- you want to boot Linux on a soft core with basic MMU support
- you need a Verilog CPU core verified against a reference ISA simulator
- you want a simple, well-documented RISC-V core for ASIC or FPGA prototyping

## When to avoid
- you need higher performance with branch prediction and dual-issue (use biriscv instead)
- you need RV64 or the atomic (A) extension in hardware
- you want a software-only emulator rather than a hardware core
- you need a fully verified, production-grade commercial CPU core

## Facets
- artifact type: library
- maturity: stable
- function: simulation, embedded
- domain: hardware, developer-tools
- platform: cross-platform
- tags: risc-v, cpu-core, verilog, rv32im, instruction-set-simulator, asic, synthesizable, pipeline-processor, processors, fpga, verilator

## Member repositories
- ultraembedded/riscv (main) score 32

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:34.015448+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:26:04.601640+00:00, confidence not recorded.
  - readme: https://github.com/ultraembedded/riscv (fetched 2026-08-28T04:05:34.015448+00:00, sha f84b5ea13a78)
- Data as of 2026-08-30T08:39:29.467469+00:00.