pConst/basic_verilog

Health v2 · maintenance only

Flags: no_releases no_license

Adoption not part of the score

2015 stars · 422 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A collection of reusable, synthesizable Verilog/SystemVerilog modules for FPGA projects, including UART, SPI, FIFO, PWM, debounce, synchronizers, and more. It also bundles vendor templates, soft processor sources, and TCL/build scripts for Xilinx and Altera workflows.

Use cases

• find a verilog uart tx/rx module for my fpga project
• reusable systemverilog fifo implementation
• debounce and synchronizer modules for fpga buttons
• spi master verilog module
• pwm generator verilog code
• axi and avalon-mm master slave templates
• tcl scripts for xilinx vivado and intel hls builds
• picoblaze soft processor sources

When to choose

• you need small, well-documented, synthesizable building blocks for an FPGA design
• you target mainstream vendors like Xilinx or Altera/Intel
• you want example project boilerplates and FPGA build scripts

When to avoid

• you need a full verified IP core with formal guarantees for safety-critical designs
• you need ASIC-grade, vendor-supported IP with licensing and support
• you work outside HDL/FPGA development

Facets

library · maturity active

developer-tools simulation embedded embedded-systems hardware developer-tools cross-platform verilog systemverilog fpga rtl uart spi fifo pwm xilinx altera hdl

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