# pConst/basic_verilog

Must-have verilog systemverilog modules

Repository: https://github.com/pConst/basic_verilog
Canonical: https://ross.abutalabs.com/products/basic_verilog
Language: Verilog
License Family: other
Topics: fpga, delay, debounce, encoder, xilinx, altera, verilog, fifo, tcl, spi-master, synchronizer, pwm, uart, uart-protocol, uart-verilog, uart-tx, uart-receiver, uart-controller, spi-interface, hls
Last push: 2026-03-12T08:19:20+00:00

## Health v2 (maintenance only)
Score: 64/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 71, release rhythm 35, longevity 100
- inputs: {"age_days": 3915, "days_push": 174, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 2015, forks 422 (observed 2026-08-28T04:06:05.497780+00:00)

## What it is
A collection of reusable, synthesizable Verilog/SystemVerilog modules for FPGA projects, including UART, SPI, FIFO, PWM, debounce, synchronizers, and more. It also bundles vendor templates, soft processor sources, and TCL/build scripts for Xilinx and Altera workflows.

## Use cases
- find a verilog uart tx/rx module for my fpga project
- reusable systemverilog fifo implementation
- debounce and synchronizer modules for fpga buttons
- spi master verilog module
- pwm generator verilog code
- axi and avalon-mm master slave templates
- tcl scripts for xilinx vivado and intel hls builds
- picoblaze soft processor sources

## When to choose
- you need small, well-documented, synthesizable building blocks for an FPGA design
- you target mainstream vendors like Xilinx or Altera/Intel
- you want example project boilerplates and FPGA build scripts

## When to avoid
- you need a full verified IP core with formal guarantees for safety-critical designs
- you need ASIC-grade, vendor-supported IP with licensing and support
- you work outside HDL/FPGA development

## Facets
- artifact type: library
- maturity: active
- function: developer-tools, simulation, embedded
- domain: embedded-systems, hardware, developer-tools
- platform: cross-platform
- tags: verilog, systemverilog, fpga, rtl, uart, spi, fifo, pwm, xilinx, altera, hdl

## Member repositories
- pConst/basic_verilog (main) score 64

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:06:05.497780+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:00:43.912188+00:00, confidence not recorded.
  - readme: https://github.com/pConst/basic_verilog (fetched 2026-08-28T04:06:05.497780+00:00, sha ca88675ee942)
- Data as of 2026-08-30T08:39:29.467469+00:00.