ZipCPU/zipcpu

Health v2 · maintenance only

Flags: no_releases no_license

Adoption not part of the score

1576 stars · 181 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

ZipCPU is a small, lightweight 32-bit RISC CPU soft core written in Verilog for FPGA deployment, with its own instruction set (not RISC-V), pipelined architecture, and Wishbone/AXI bus support. The repository includes the CPU core, documentation, and an associated toolchain.

Use cases

• embed a small RISC CPU in an FPGA design
• learn how a pipelined RISC CPU is implemented in Verilog
• simulate a soft-core CPU with Verilator
• build a custom SoC with a Wishbone or AXI4-Lite bus
• use a lightweight open-source CPU with its own toolchain

When to choose

• you need a compact, open-source 32-bit soft core for an FPGA project
• you want a CPU with dual register sets for simple interrupt handling
• you prefer a simple custom ISA over RISC-V for learning or embedded control

When to avoid

• you need RISC-V compatibility or an existing RISC-V software ecosystem
• you require a floating point unit (not yet implemented)
• you need a high-performance out-of-order or superscalar processor

Facets

library · maturity active

embedded hardware embedded-systems cross-platform risc-cpu soft-core verilog fpga wishbone axi4 verilator cross-compiler pipelined-cpu

Member repositories

For agents

markdown · JSON · MCP: product_card(name="ZipCPU/zipcpu")