# ZipCPU/zipcpu

A small, light weight, RISC CPU soft core

Repository: https://github.com/ZipCPU/zipcpu
Canonical: https://ross.abutalabs.com/products/zipcpu
Language: Verilog
License Family: other
Topics: fpga, soft-core, cross-compiler, verilog, verilator, wishbone, wishbone-bus, zipcpu, cpu, risc-cpu
Last push: 2026-08-19T12:02:29+00:00

## Health v2 (maintenance only)
Score: 76/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 98, release rhythm 35, longevity 100
- inputs: {"age_days": 3633, "days_push": 14, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1576, forks 181 (observed 2026-08-28T04:05:06.061315+00:00)

## What it is
ZipCPU is a small, lightweight 32-bit RISC CPU soft core written in Verilog for FPGA deployment, with its own instruction set (not RISC-V), pipelined architecture, and Wishbone/AXI bus support. The repository includes the CPU core, documentation, and an associated toolchain.

## Use cases
- embed a small RISC CPU in an FPGA design
- learn how a pipelined RISC CPU is implemented in Verilog
- simulate a soft-core CPU with Verilator
- build a custom SoC with a Wishbone or AXI4-Lite bus
- use a lightweight open-source CPU with its own toolchain

## When to choose
- you need a compact, open-source 32-bit soft core for an FPGA project
- you want a CPU with dual register sets for simple interrupt handling
- you prefer a simple custom ISA over RISC-V for learning or embedded control

## When to avoid
- you need RISC-V compatibility or an existing RISC-V software ecosystem
- you require a floating point unit (not yet implemented)
- you need a high-performance out-of-order or superscalar processor

## Facets
- artifact type: library
- maturity: active
- function: embedded
- domain: hardware, embedded-systems
- platform: cross-platform
- tags: risc-cpu, soft-core, verilog, fpga, wishbone, axi4, verilator, cross-compiler, pipelined-cpu

## Member repositories
- ZipCPU/zipcpu (main) score 76

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:06.061315+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:57:14.152168+00:00, confidence not recorded.
  - readme: https://github.com/ZipCPU/zipcpu (fetched 2026-08-28T04:05:06.061315+00:00, sha cdfc46600ad3)
- Data as of 2026-08-30T08:39:29.467469+00:00.