google/xls

Health v2 · maintenance only

Adoption not part of the score

1837 stars · 273 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

XLS is Google's High Level Synthesis toolchain that compiles high-level functional descriptions into synthesizable Verilog/SystemVerilog hardware designs. Designs can also run as efficient native host software, with tooling to help formally verify equivalence between the two.

Use cases

• generate verilog from a high-level hardware description
• compile dsl code to synthesizable rtl
• prototype hardware ip that also runs as host software
• pipeline a datapath for fpga or asic
• formally verify hardware matches its software model
• model stateful concurrent hardware processes

When to choose

• you want to write hardware logic in a high-level language instead of raw Verilog
• you need one source of truth for both simulation software and hardware blocks
• you are doing hardware/software co-design for accelerators or custom IP
• you want pipelined functions or stateful processes compiled to RTL

When to avoid

• you need a mature, production-hardened synthesis flow with vendor support
• you require full support for complex existing RTL or mixed-language integration
• you cannot tolerate bugs and sharp edges in an early-stage tool
• you only need simulation of existing Verilog rather than synthesis from a high-level description

Facets

library · maturity experimental

compiler sdk simulation testing hardware embedded-systems compilers developer-tools cpp cli high-level-synthesis hls verilog systemverilog fpga hardware-design dsl formal-verification pipelining linux

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markdown · JSON · MCP: product_card(name="google/xls")