# google/xls

XLS: Accelerated HW Synthesis

Repository: https://github.com/google/xls
Canonical: https://ross.abutalabs.com/products/xls
Homepage: http://google.github.io/xls/
Language: C++
License: Apache-2.0
License Family: permissive
Topics: compiler, high-level-synthesis, hls, open-source, pipeline, verilog, mid-level-synthesis
Last push: 2026-08-26T18:59:51+00:00

## Health v2 (maintenance only)
Score: 95/100 (v2, computed 2026-09-03T02:39:23.370411+00:00)
- activity 99, release rhythm 87, longevity 100
- inputs: {"age_days": 2309, "days_push": 7, "days_rel": 7, "gap_med": 1, "n_releases_24m": 458}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1837, forks 273 (observed 2026-08-28T04:05:42.711828+00:00)

## What it is
XLS is Google's High Level Synthesis toolchain that compiles high-level functional descriptions into synthesizable Verilog/SystemVerilog hardware designs. Designs can also run as efficient native host software, with tooling to help formally verify equivalence between the two.

## Use cases
- generate verilog from a high-level hardware description
- compile dsl code to synthesizable rtl
- prototype hardware ip that also runs as host software
- pipeline a datapath for fpga or asic
- formally verify hardware matches its software model
- model stateful concurrent hardware processes

## When to choose
- you want to write hardware logic in a high-level language instead of raw Verilog
- you need one source of truth for both simulation software and hardware blocks
- you are doing hardware/software co-design for accelerators or custom IP
- you want pipelined functions or stateful processes compiled to RTL

## When to avoid
- you need a mature, production-hardened synthesis flow with vendor support
- you require full support for complex existing RTL or mixed-language integration
- you cannot tolerate bugs and sharp edges in an early-stage tool
- you only need simulation of existing Verilog rather than synthesis from a high-level description

## Facets
- artifact type: library
- maturity: experimental
- function: compiler, sdk, simulation, testing
- domain: hardware, embedded-systems, compilers, developer-tools
- platform: cpp, cli
- tags: high-level-synthesis, hls, verilog, systemverilog, fpga, hardware-design, dsl, formal-verification, pipelining, linux

## Member repositories
- google/xls (main) score 95

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:42.711828+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T08:19:40.675770+00:00, confidence not recorded.
  - readme: https://github.com/google/xls (fetched 2026-08-28T04:05:42.711828+00:00, sha 91fbc2364460)
  - homepage: http://google.github.io/xls/ (fetched 2026-08-29T10:57:26.074328+00:00, sha b4c139833285)
- Data as of 2026-08-30T08:39:29.467469+00:00.