verilog-to-routing/vtr-verilog-to-routing

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1261 stars · 446 forks observed · 2026-09-03

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Verilog to Routing (VTR) is an open-source CAD toolchain for FPGA research that takes a Verilog circuit description plus a target FPGA architecture description and compiles it through elaboration/synthesis (PARMYS/ODIN II), logic optimization and technology mapping (ABC), and packing, placement, routing and timing analysis (VPR) to produce FPGA speed and area results. It targets a wide range of hypothetical, commercial-like, and commercial FPGA architectures, includes benchmark designs, and can emit FASM for programming some commercial FPGAs via the F4PGA/Symbiflow flow.

Use cases

• evaluate speed and area of a custom FPGA architecture from a verilog design
• run benchmarks through an open-source FPGA place-and-route flow
• research new placement and routing algorithms for FPGAs
• synthesize verilog into a technology-mapped netlist for an FPGA fabric
• compare multiple FPGA architectures for critical path delay and area
• generate FASM/bitstream input for open-source FPGA tooling
• teach FPGA CAD concepts with modifiable open-source tools

When to choose

• you are doing FPGA architecture or CAD algorithm research and need fully open, modifiable tools
• you need reproducible timing/area metrics for hypothetical or commercial-like FPGA fabrics
• you want an open-source alternative to vendor CAD flows for place-and-route experiments
• you need bundled benchmarks to fairly evaluate architecture changes

When to avoid

• you need an ASIC physical design flow - VTR targets FPGAs only
• you require signoff-quality, vendor-supported bitstream generation for a specific commercial FPGA
• you need full SystemVerilog/UVM synthesis support - ODIN II handles a Verilog subset

Facets

framework · maturity active

compiler cli developer-tools hardware compilers developer-tools cross-platform cpp cli fpga eda cad verilog hdl synthesis place-and-route logic-synthesis technology-mapping timing-analysis packing vpr odin-ii abc fasm architecture-exploration benchmarks digital-design vlsi algorithms linux macos

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