# verilog-to-routing/vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Repository: https://github.com/verilog-to-routing/vtr-verilog-to-routing
Canonical: https://ross.abutalabs.com/products/vtr-verilog-to-routing
Homepage: https://verilogtorouting.org
Language: C++
License: NOASSERTION
License Family: other
Topics: vtr, fpga, cad, verilog, placement, routing, synthesis, eda, vpr
Last push: 2026-09-03T00:32:47+00:00

## Health v2 (maintenance only)
Score: 68/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 100, release rhythm 8, longevity 100
- inputs: {"age_days": 4086, "days_push": 0, "days_rel": 590, "gap_med": null, "n_releases_24m": 1}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1261, forks 446 (observed 2026-09-03T02:15:20.285268+00:00)

## What it is
Verilog to Routing (VTR) is an open-source CAD toolchain for FPGA research that takes a Verilog circuit description plus a target FPGA architecture description and compiles it through elaboration/synthesis (PARMYS/ODIN II), logic optimization and technology mapping (ABC), and packing, placement, routing and timing analysis (VPR) to produce FPGA speed and area results. It targets a wide range of hypothetical, commercial-like, and commercial FPGA architectures, includes benchmark designs, and can emit FASM for programming some commercial FPGAs via the F4PGA/Symbiflow flow.

## Use cases
- evaluate speed and area of a custom FPGA architecture from a verilog design
- run benchmarks through an open-source FPGA place-and-route flow
- research new placement and routing algorithms for FPGAs
- synthesize verilog into a technology-mapped netlist for an FPGA fabric
- compare multiple FPGA architectures for critical path delay and area
- generate FASM/bitstream input for open-source FPGA tooling
- teach FPGA CAD concepts with modifiable open-source tools

## When to choose
- you are doing FPGA architecture or CAD algorithm research and need fully open, modifiable tools
- you need reproducible timing/area metrics for hypothetical or commercial-like FPGA fabrics
- you want an open-source alternative to vendor CAD flows for place-and-route experiments
- you need bundled benchmarks to fairly evaluate architecture changes

## When to avoid
- you need an ASIC physical design flow - VTR targets FPGAs only
- you require signoff-quality, vendor-supported bitstream generation for a specific commercial FPGA
- you need full SystemVerilog/UVM synthesis support - ODIN II handles a Verilog subset

## Facets
- artifact type: framework
- maturity: active
- function: compiler, cli, developer-tools
- domain: hardware, compilers, developer-tools
- platform: cross-platform, cpp, cli
- tags: fpga, eda, cad, verilog, hdl, synthesis, place-and-route, logic-synthesis, technology-mapping, timing-analysis, packing, vpr, odin-ii, abc, fasm, architecture-exploration, benchmarks, digital-design, vlsi, algorithms, linux, macos

## Member repositories
- verilog-to-routing/vtr-verilog-to-routing (main) score 68

## Provenance
- Observed fields: from GitHub, fetched 2026-09-03T02:15:20.285268+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T05:07:08.978909+00:00, confidence not recorded.
  - readme: https://github.com/verilog-to-routing/vtr-verilog-to-routing (fetched 2026-09-03T02:15:20.285268+00:00, sha 37878044309e)
  - homepage: https://verilogtorouting.org (fetched 2026-08-29T12:17:47.843594+00:00, sha 73a9e247104f)
- Data as of 2026-08-30T08:39:29.467469+00:00.