eugene-tarassov/vivado-risc-v

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

1091 stars · 249 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A collection of Xilinx Vivado block designs and Tcl scripts that generate a RISC-V SoC FPGA bitstream capable of booting a full Debian Linux distribution. It supports multiple AMD/Digilent FPGA boards and includes OpenSBI, U-Boot, Linux kernel, and Debian root filesystem on a bootable SD card.

Use cases

• boot Debian Linux on an FPGA RISC-V SoC
• prototype a RISC-V Linux server on a Xilinx FPGA
• build a RISC-V SoC bitstream with Vivado
• run bare-metal or RTOS software on RISC-V hardware
• validate RISC-V debugging over JTAG
• experiment with Rocket Chip or BOOM cores on FPGA

When to choose

• you own one of the supported Xilinx/Digilent FPGA boards and want a working RISC-V Linux system
• you need a reference design for RISC-V software development and debugging
• you want to prototype RISC-V SoCs with full Debian package availability

When to avoid

• you don't have access to supported FPGA hardware
• you need a synthesis tool other than AMD/Xilinx Vivado/Vitis
• you want a lightweight RISC-V emulator rather than real hardware

Facets

application · maturity active

embedded compiler developer-tools simulation embedded-systems hardware operating-systems developer-tools fpga risc-v soc vivado debian rocket-chip boom opensbi u-boot bitstream nexys-video arty-a7 vc707 kc705 genesys2 linux xilinx

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markdown · JSON · MCP: product_card(name="eugene-tarassov/vivado-risc-v")