# eugene-tarassov/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Repository: https://github.com/eugene-tarassov/vivado-risc-v
Canonical: https://ross.abutalabs.com/products/vivado-risc-v
Language: Tcl
License: NOASSERTION
License Family: other
Topics: nexys-video, risc-v, linux, xilinx, vivado, fpga, vc707, genesys2, boom, rocketchip, kc705, arty-a7, riscv
Last push: 2026-07-13T07:23:28+00:00

## Health v2 (maintenance only)
Score: 83/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 92, release rhythm 61, longevity 100
- inputs: {"age_days": 2392, "days_push": 51, "days_rel": 51, "gap_med": 360, "n_releases_24m": 2}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1091, forks 249 (observed 2026-08-28T04:03:33.144921+00:00)

## What it is
A collection of Xilinx Vivado block designs and Tcl scripts that generate a RISC-V SoC FPGA bitstream capable of booting a full Debian Linux distribution. It supports multiple AMD/Digilent FPGA boards and includes OpenSBI, U-Boot, Linux kernel, and Debian root filesystem on a bootable SD card.

## Use cases
- boot Debian Linux on an FPGA RISC-V SoC
- prototype a RISC-V Linux server on a Xilinx FPGA
- build a RISC-V SoC bitstream with Vivado
- run bare-metal or RTOS software on RISC-V hardware
- validate RISC-V debugging over JTAG
- experiment with Rocket Chip or BOOM cores on FPGA

## When to choose
- you own one of the supported Xilinx/Digilent FPGA boards and want a working RISC-V Linux system
- you need a reference design for RISC-V software development and debugging
- you want to prototype RISC-V SoCs with full Debian package availability

## When to avoid
- you don't have access to supported FPGA hardware
- you need a synthesis tool other than AMD/Xilinx Vivado/Vitis
- you want a lightweight RISC-V emulator rather than real hardware

## Facets
- artifact type: application
- maturity: active
- function: embedded, compiler, developer-tools, simulation
- domain: embedded-systems, hardware, operating-systems, developer-tools
- platform: -
- tags: fpga, risc-v, soc, vivado, debian, rocket-chip, boom, opensbi, u-boot, bitstream, nexys-video, arty-a7, vc707, kc705, genesys2, linux, xilinx

## Member repositories
- eugene-tarassov/vivado-risc-v (main) score 83

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:33.144921+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:49:07.759495+00:00, confidence not recorded.
  - readme: https://github.com/eugene-tarassov/vivado-risc-v (fetched 2026-08-28T04:03:33.144921+00:00, sha bd82776dafd1)
- Data as of 2026-08-30T08:39:29.467469+00:00.