veryl-lang/veryl

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

1028 stars · 71 forks observed · 2026-09-03

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Veryl is a modern hardware description language based on SystemVerilog, with a Rust-implemented compiler that transpiles Veryl source into readable SystemVerilog. It ships a full toolchain including a package manager, build tool, formatter, real-time linter, and editor integrations for VSCode, Vim, and Emacs.

Use cases

• write RTL in a modern HDL instead of SystemVerilog
• transpile hardware description code to readable SystemVerilog
• gradually replace parts of an existing SystemVerilog project
• guarantee synthesizable, simulation-consistent RTL code
• format and lint Verilog-family hardware code
• manage dependencies and builds for FPGA/ASIC logic design

When to choose

• you want a cleaner, safer syntax than SystemVerilog while keeping full interoperability
• you need readable generated SystemVerilog for debugging or mixed projects
• you want an integrated toolchain (package manager, formatter, editor support) for HDL work

When to avoid

• you need a mature, industry-standard HDL with guaranteed tool vendor support
• your team cannot adopt a language still in the language-design exploration phase
• you require direct synthesis of Veryl without going through generated SystemVerilog

Facets

cli-tool · maturity active

compiler parser build-tool package-manager formatter linter developer-tools hardware programming-languages compilers developer-tools embedded-systems cross-platform cli windows rust hardware-description-language systemverilog verilog rtl transpiler fpga asic logic-design language-server linux macos

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