# veryl-lang/veryl

Veryl: A Modern Hardware Description Language

Repository: https://github.com/veryl-lang/veryl
Canonical: https://ross.abutalabs.com/products/veryl
Language: Rust
License: NOASSERTION
License Family: other
Topics: rtl, rust, systemverilog, verilog, hdl
Last push: 2026-09-02T12:57:58+00:00

## Health v2 (maintenance only)
Score: 99/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 100, release rhythm 100, longevity 97
- inputs: {"age_days": 1364, "days_push": 0, "days_rel": 0, "gap_med": 29, "n_releases_24m": 26}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1028, forks 71 (observed 2026-09-03T02:15:20.293734+00:00)

## What it is
Veryl is a modern hardware description language based on SystemVerilog, with a Rust-implemented compiler that transpiles Veryl source into readable SystemVerilog. It ships a full toolchain including a package manager, build tool, formatter, real-time linter, and editor integrations for VSCode, Vim, and Emacs.

## Use cases
- write RTL in a modern HDL instead of SystemVerilog
- transpile hardware description code to readable SystemVerilog
- gradually replace parts of an existing SystemVerilog project
- guarantee synthesizable, simulation-consistent RTL code
- format and lint Verilog-family hardware code
- manage dependencies and builds for FPGA/ASIC logic design

## When to choose
- you want a cleaner, safer syntax than SystemVerilog while keeping full interoperability
- you need readable generated SystemVerilog for debugging or mixed projects
- you want an integrated toolchain (package manager, formatter, editor support) for HDL work

## When to avoid
- you need a mature, industry-standard HDL with guaranteed tool vendor support
- your team cannot adopt a language still in the language-design exploration phase
- you require direct synthesis of Veryl without going through generated SystemVerilog

## Facets
- artifact type: cli-tool
- maturity: active
- function: compiler, parser, build-tool, package-manager, formatter, linter, developer-tools
- domain: hardware, programming-languages, compilers, developer-tools, embedded-systems
- platform: cross-platform, cli, windows, rust
- tags: hardware-description-language, systemverilog, verilog, rtl, transpiler, fpga, asic, logic-design, language-server, linux, macos

## Member repositories
- veryl-lang/veryl (main) score 99

## Provenance
- Observed fields: from GitHub, fetched 2026-09-03T02:15:20.293734+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T07:08:00.555652+00:00, confidence not recorded.
  - readme: https://github.com/veryl-lang/veryl (fetched 2026-09-03T02:15:20.293734+00:00, sha 547f8a3e4417)
  - registry_crates: https://crates.io/api/v1/crates/veryl (fetched 2026-08-29T13:08:12.635224+00:00, sha 1e5083811955)
- Data as of 2026-08-30T08:39:29.467469+00:00.