verilator/verilator

Health v2 · maintenance only

Flags: no_releases no_license

Adoption not part of the score

3876 stars · 887 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

Verilator is an open-source Verilog/SystemVerilog simulator and lint system that compiles RTL designs into fast, multithreaded C++ or SystemC models. It is one of the leading SystemVerilog simulators, widely used in industry and academia for high-performance simulation and code-quality checking.

Use cases

• simulate verilog rtl designs fast
• lint systemverilog code for quality checks
• convert systemverilog to c++ or systemc models
• run cycle-accurate soc simulation
• verify risc-v or arm ip with open-source tools
• generate coverage and assertion checks for rtl
• replace expensive commercial verilog simulators

When to choose

• you need the fastest open-source verilog/systemverilog simulation
• you want to lint rtl code in CI pipelines
• you need to migrate SystemVerilog designs to C++/SystemC
• you are verifying RISC-V or Arm IP on a budget
• you want multithreaded simulation performance

When to avoid

• you need full event-driven IEEE 1800 compliance with SDF annotation
• you require mixed-signal (analog) simulation
• you rely on tristate buses and unknown (x) propagation heavily
• you need a closed-source vendor's full verification feature set

Facets

cli-tool · maturity stable

compiler simulation linter parser developer-tools hardware developer-tools simulation embedded-systems windows cpp cli verilog systemverilog rtl-simulation systemc fpga asic-verification hardware-design lint linux macos

Member repositories

For agents

markdown · JSON · MCP: product_card(name="verilator/verilator")