# verilator/verilator

Verilator open-source SystemVerilog simulator and lint system

Repository: https://github.com/verilator/verilator
Canonical: https://ross.abutalabs.com/products/verilator
Homepage: https://verilator.org
Language: SystemVerilog
License: NOASSERTION
License Family: other
Topics: verilog, system-verilog, verilog-simulator, verilator, compilers, cpp, systemc, rtl
Last push: 2026-08-26T15:05:12+00:00

## Health v2 (maintenance only)
Score: 77/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 35, longevity 100
- inputs: {"age_days": 2638, "days_push": 7, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3876, forks 887 (observed 2026-08-28T04:08:27.897773+00:00)

## What it is
Verilator is an open-source Verilog/SystemVerilog simulator and lint system that compiles RTL designs into fast, multithreaded C++ or SystemC models. It is one of the leading SystemVerilog simulators, widely used in industry and academia for high-performance simulation and code-quality checking.

## Use cases
- simulate verilog rtl designs fast
- lint systemverilog code for quality checks
- convert systemverilog to c++ or systemc models
- run cycle-accurate soc simulation
- verify risc-v or arm ip with open-source tools
- generate coverage and assertion checks for rtl
- replace expensive commercial verilog simulators

## When to choose
- you need the fastest open-source verilog/systemverilog simulation
- you want to lint rtl code in CI pipelines
- you need to migrate SystemVerilog designs to C++/SystemC
- you are verifying RISC-V or Arm IP on a budget
- you want multithreaded simulation performance

## When to avoid
- you need full event-driven IEEE 1800 compliance with SDF annotation
- you require mixed-signal (analog) simulation
- you rely on tristate buses and unknown (x) propagation heavily
- you need a closed-source vendor's full verification feature set

## Facets
- artifact type: cli-tool
- maturity: stable
- function: compiler, simulation, linter, parser, developer-tools
- domain: hardware, developer-tools, simulation, embedded-systems
- platform: windows, cpp, cli
- tags: verilog, systemverilog, rtl-simulation, systemc, fpga, asic-verification, hardware-design, lint, linux, macos

## Member repositories
- verilator/verilator (main) score 77

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:27.897773+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:25:45.764094+00:00, confidence not recorded.
  - readme: https://github.com/verilator/verilator (fetched 2026-08-28T04:08:27.897773+00:00, sha fc3848a6ddff)
  - homepage: https://verilator.org (fetched 2026-08-29T09:20:12.945076+00:00, sha e68babed7833)
  - site_page: https://veripool.org/verilator/documentation (fetched 2026-08-29T09:20:12.954178+00:00, sha b9d91a92ce4c)
  - site_page: https://veripool.org/guide/latest/faq.html (fetched 2026-08-29T09:20:12.956281+00:00, sha 862356c2acd4)
  - site_page: https://veripool.org/about (fetched 2026-08-29T09:20:12.964847+00:00, sha 2c9056e34697)
  - site_page: https://veripool.org/verilog-mode/faq (fetched 2026-08-29T09:20:12.958449+00:00, sha fef06776de97)
  - site_page: https://veripool.org/verilog-mode/help (fetched 2026-08-29T09:20:12.961236+00:00, sha e5e005fc4301)
- Data as of 2026-08-30T08:39:29.467469+00:00.