tiny-tpu-v2/tiny-tpu

Health v2 · maintenance only

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1367 stars · 110 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A minimal tensor processing unit (TPU) written in Verilog, reinvented from Google's TPU V1/V2 architectures. It includes a systolic array of processing elements, a vector processing unit, unified buffer, and control unit, with FPGA demos (MNIST, XOR) and an ASIC-hardened variant.

Use cases

• learn how a TPU works at the RTL level
• simulate a systolic array matrix multiplier in Verilog
• run an MNIST inference demo on an FPGA
• harden a TPU design for ASIC tapeout with OpenLane
• study fixed-point arithmetic in hardware
• build custom hardware modules for a tensor accelerator

When to choose

• you want an educational, readable TPU implementation in Verilog
• you have an Intel DE1-SoC FPGA board and want a working accelerator demo
• you need a starting point for systolic array or ASIC hardware projects

When to avoid

• you need a production-grade, high-performance TPU or GPU
• you want software-only ML acceleration without FPGA/ASIC hardware
• you need a licensed, commercially supported IP core (the project has no license file)

Facets

library · maturity active

machine-learning simulation developer-tools hardware machine-learning embedded-systems education cross-platform verilog fpga systolic-array asic rtl hardware-design tpu openlane quartus

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