# tiny-tpu-v2/tiny-tpu

A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1

Repository: https://github.com/tiny-tpu-v2/tiny-tpu
Canonical: https://ross.abutalabs.com/products/tiny-tpu
Language: Verilog
License Family: other
Last push: 2026-04-03T20:22:36+00:00

## Health v2 (maintenance only)
Score: 53/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 75, release rhythm 35, longevity 33
- inputs: {"age_days": 471, "days_push": 152, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1367, forks 110 (observed 2026-08-28T04:04:31.518045+00:00)

## What it is
A minimal tensor processing unit (TPU) written in Verilog, reinvented from Google's TPU V1/V2 architectures. It includes a systolic array of processing elements, a vector processing unit, unified buffer, and control unit, with FPGA demos (MNIST, XOR) and an ASIC-hardened variant.

## Use cases
- learn how a TPU works at the RTL level
- simulate a systolic array matrix multiplier in Verilog
- run an MNIST inference demo on an FPGA
- harden a TPU design for ASIC tapeout with OpenLane
- study fixed-point arithmetic in hardware
- build custom hardware modules for a tensor accelerator

## When to choose
- you want an educational, readable TPU implementation in Verilog
- you have an Intel DE1-SoC FPGA board and want a working accelerator demo
- you need a starting point for systolic array or ASIC hardware projects

## When to avoid
- you need a production-grade, high-performance TPU or GPU
- you want software-only ML acceleration without FPGA/ASIC hardware
- you need a licensed, commercially supported IP core (the project has no license file)

## Facets
- artifact type: library
- maturity: active
- function: machine-learning, simulation, developer-tools
- domain: hardware, machine-learning, embedded-systems, education
- platform: cross-platform
- tags: verilog, fpga, systolic-array, asic, rtl, hardware-design, tpu, openlane, quartus

## Member repositories
- tiny-tpu-v2/tiny-tpu (main) score 53

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:31.518045+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:41:09.763221+00:00, confidence not recorded.
  - readme: https://github.com/tiny-tpu-v2/tiny-tpu (fetched 2026-08-28T04:04:31.518045+00:00, sha cdd25b547696)
- Data as of 2026-08-30T08:39:29.467469+00:00.