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sin-x/FPGA resource

数字IC相关资料 observed · 2026-08-28

github.com/sin-x/FPGA observed · 2026-08-28

Health v2 · maintenance only

45/100

  • Activity 29
  • Release rhythm 35
  • Longevity 100

Flags: no_releases no_license

How is this computed?

round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10) — computed 2026-09-02. Adoption (stars, forks) is never an input.

  • gap_med: n/a
  • age_days: 2256
  • days_rel: n/a
  • days_push: 428
  • n_releases_24m: 0

Full methodology

Adoption not part of the score

1579 stars · 369 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A curated collection of notes, PDFs, links, and study materials on digital IC design, covering FPGA principles, static timing analysis, clock domain crossing, low power, SystemVerilog verification, and interview questions. It is a Chinese-language knowledge repository rather than executable software.

Use cases

  • learn FPGA design fundamentals
  • study static timing analysis and timing constraints
  • prepare for digital IC design interviews
  • understand clock domain crossing and async FIFO design
  • find SystemVerilog verification resources
  • review digital logic and DSP concepts

When to choose

  • you are studying digital IC or FPGA design and want curated notes and references
  • you are preparing for IC design written tests and interviews
  • you want a single index of CDC, STA, and verification materials

When to avoid

  • you need runnable code, tools, or libraries rather than study notes
  • you need English-language documentation only
  • you need an official or peer-reviewed curriculum

Facets

learning-resource · maturity active

documentation developer-tools hardware education embedded-systems cross-platform fpga digital-ic verilog systemverilog static-timing-analysis clock-domain-crossing interview-preparation notes-collection awesome-list

1 source

Member repositories

RepositoryRoleHealth v2
sin-x/FPGAmain45

For agents

markdown · JSON · MCP: product_card(name="sin-x/FPGA")

Data as of 2026-08-30T08:39:29.467469+00:00 · Report a problem