olofk/serv

Health v2 · maintenance only

Adoption not part of the score

1875 stars · 262 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

SERV is an award-winning bit-serial RISC-V CPU core written in Verilog, claimed to be the world's smallest RISC-V CPU at around 200 LUTs on FPGAs and ~2.1kGE in CMOS. It is designed for integration into FPGA and ASIC designs where silicon real estate is at a premium, with extensive documentation and a reference SoC (Servant) for running Zephyr RTOS.

Use cases

• add a tiny RISC-V CPU to an FPGA design with minimal LUT usage
• integrate a soft core into an ASIC where gate count is critical
• run Zephyr RTOS on a minimal RISC-V SoC
• run many RISC-V cores in parallel on a single FPGA board
• learn how a bit-serial CPU works with gate-level documentation
• run the RISC-V compliance regression test suite

When to choose

• you need a RISC-V core with the smallest possible footprint on FPGA or ASIC
• performance is not critical but area is at a premium
• you want well-documented, open-source (ISC) CPU core for hardware projects

When to avoid

• you need high performance or fast execution, since bit-serial execution is very slow
• you need a full-featured application-class processor with caches and MMU
• you are not comfortable integrating Verilog RTL into your build flow

Facets

library · maturity active

embedded programming-language embedded-systems hardware risc-v cpu-core bit-serial fpga asic verilog hardware-design soc

Member repositories

For agents

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