# olofk/serv

SERV - The SErial RISC-V CPU

Repository: https://github.com/olofk/serv
Canonical: https://ross.abutalabs.com/products/serv
Language: Verilog
License: ISC
License Family: permissive
Topics: verilog, fpga, asic, risc-v
Last push: 2026-08-25T12:38:55+00:00

## Health v2 (maintenance only)
Score: 72/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 99, release rhythm 20, longevity 100
- inputs: {"age_days": 2863, "days_push": 8, "days_rel": 322, "gap_med": 265, "n_releases_24m": 2}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1875, forks 262 (observed 2026-08-28T04:05:47.595135+00:00)

## What it is
SERV is an award-winning bit-serial RISC-V CPU core written in Verilog, claimed to be the world's smallest RISC-V CPU at around 200 LUTs on FPGAs and ~2.1kGE in CMOS. It is designed for integration into FPGA and ASIC designs where silicon real estate is at a premium, with extensive documentation and a reference SoC (Servant) for running Zephyr RTOS.

## Use cases
- add a tiny RISC-V CPU to an FPGA design with minimal LUT usage
- integrate a soft core into an ASIC where gate count is critical
- run Zephyr RTOS on a minimal RISC-V SoC
- run many RISC-V cores in parallel on a single FPGA board
- learn how a bit-serial CPU works with gate-level documentation
- run the RISC-V compliance regression test suite

## When to choose
- you need a RISC-V core with the smallest possible footprint on FPGA or ASIC
- performance is not critical but area is at a premium
- you want well-documented, open-source (ISC) CPU core for hardware projects

## When to avoid
- you need high performance or fast execution, since bit-serial execution is very slow
- you need a full-featured application-class processor with caches and MMU
- you are not comfortable integrating Verilog RTL into your build flow

## Facets
- artifact type: library
- maturity: active
- function: embedded, programming-language
- domain: embedded-systems, hardware
- platform: -
- tags: risc-v, cpu-core, bit-serial, fpga, asic, verilog, hardware-design, soc

## Member repositories
- olofk/serv (main) score 72

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:47.595135+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:14:46.586731+00:00, confidence not recorded.
  - readme: https://github.com/olofk/serv (fetched 2026-08-28T04:05:47.595135+00:00, sha 0f5540c3f06e)
- Data as of 2026-08-30T08:39:29.467469+00:00.