rsd-devel/rsd

Health v2 · maintenance only

Adoption not part of the score

1195 stars · 122 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

RSD is a 32-bit RISC-V out-of-order superscalar processor core written in SystemVerilog. It is designed for high performance with aggressive OoO features while remaining compact enough to synthesize for small FPGAs such as the Xilinx Zynq.

Use cases

• simulate an out-of-order RISC-V processor core in Verilator or QuestaSim
• synthesize a compact superscalar CPU core for a small FPGA
• run Zephyr RTOS applications on a custom RISC-V core
• study out-of-order microarchitecture with pipeline visualization via Konata
• deploy a RISC-V processor on a Xilinx Zynq Zedboard
• experiment with configurable OoO pipeline parameters like issue width and in-flight instructions

When to choose

• you need a compact, FPGA-synthesizable out-of-order RISC-V core
• you want to learn or research OoO superscalar microarchitecture in SystemVerilog
• you target Xilinx Zynq boards and need AXI4 bus support
• you need a core that runs Zephyr applications

When to avoid

• you need a 64-bit RISC-V core (RSD is RV32IMF only)
• you need a production-proven, silicon-verified CPU for commercial products
• you want a simple in-order core for minimal resource usage
• you need Linux-capable application processors with MMU support

Facets

library · maturity active

simulation embedded hardware risc-v out-of-order superscalar systemverilog processor-core fpga verilator cpu-implementation computer-architecture processors linux xilinx-zynq

Member repositories

For agents

markdown · JSON · MCP: product_card(name="rsd-devel/rsd")