# rsd-devel/rsd

RSD: RISC-V Out-of-Order Superscalar Processor

Repository: https://github.com/rsd-devel/rsd
Canonical: https://ross.abutalabs.com/products/rsd
Language: SystemVerilog
License: Apache-2.0
License Family: permissive
Last push: 2026-08-18T07:25:09+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 98, release rhythm 8, longevity 100
- inputs: {"age_days": 2457, "days_push": 15, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1195, forks 122 (observed 2026-08-28T04:03:56.782478+00:00)

## What it is
RSD is a 32-bit RISC-V out-of-order superscalar processor core written in SystemVerilog. It is designed for high performance with aggressive OoO features while remaining compact enough to synthesize for small FPGAs such as the Xilinx Zynq.

## Use cases
- simulate an out-of-order RISC-V processor core in Verilator or QuestaSim
- synthesize a compact superscalar CPU core for a small FPGA
- run Zephyr RTOS applications on a custom RISC-V core
- study out-of-order microarchitecture with pipeline visualization via Konata
- deploy a RISC-V processor on a Xilinx Zynq Zedboard
- experiment with configurable OoO pipeline parameters like issue width and in-flight instructions

## When to choose
- you need a compact, FPGA-synthesizable out-of-order RISC-V core
- you want to learn or research OoO superscalar microarchitecture in SystemVerilog
- you target Xilinx Zynq boards and need AXI4 bus support
- you need a core that runs Zephyr applications

## When to avoid
- you need a 64-bit RISC-V core (RSD is RV32IMF only)
- you need a production-proven, silicon-verified CPU for commercial products
- you want a simple in-order core for minimal resource usage
- you need Linux-capable application processors with MMU support

## Facets
- artifact type: library
- maturity: active
- function: simulation, embedded
- domain: hardware
- platform: -
- tags: risc-v, out-of-order, superscalar, systemverilog, processor-core, fpga, verilator, cpu-implementation, computer-architecture, processors, linux, xilinx-zynq

## Member repositories
- rsd-devel/rsd (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:56.782478+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:22:07.293071+00:00, confidence not recorded.
  - readme: https://github.com/rsd-devel/rsd (fetched 2026-08-28T04:03:56.782478+00:00, sha f46d76e9d5e9)
- Data as of 2026-08-30T08:39:29.467469+00:00.