pulp-platform/pulpino

Health v2 · maintenance only

Flags: no_releases no_license

Adoption not part of the score

1062 stars · 325 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

PULPino is an open-source single-core 32-bit RISC-V microcontroller system developed at ETH Zurich, configurable with either the RISCY or zero-riscy core. It includes a rich set of peripherals (I2C, SPI, I2S, UART), supports RTL simulation, FPGA deployment, and was taped out as an ASIC in 65nm.

Use cases

• build a RISC-V microcontroller system for embedded projects
• simulate a RISC-V SoC in RTL before FPGA or ASIC implementation
• develop ultra-low-power IoT applications on an open hardware platform
• learn RISC-V architecture and microcontroller design
• run bare-metal C programs on a RISC-V core with JTAG debugging
• evaluate RISCY vs zero-riscy cores for energy-efficient signal processing

When to choose

• you need an open-source, silicon-proven RISC-V microcontroller platform
• you want to prototype on FPGA or simulate RTL with ModelSim
• you target ultra-low-power or ultra-low-area embedded applications
• you want full debug support and peripheral access (I2C, SPI, UART, I2S)

When to avoid

• you need multi-core support or µDMA - use PULPissimo instead
• you need a modern, actively developed platform - PULPino is in maintenance mode
• you need a high-performance application processor rather than a microcontroller
• you cannot work with SystemVerilog RTL and simulation toolchains

Facets

application · maturity maintenance

embedded simulation developer-tools embedded-systems hardware autonomous-vehicles embedded cli risc-v microcontroller systemverilog fpga rtl-simulation ultra-low-power iot soc linux

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markdown · JSON · MCP: product_card(name="pulp-platform/pulpino")