# pulp-platform/pulpino

An open-source microcontroller system based on RISC-V

Repository: https://github.com/pulp-platform/pulpino
Canonical: https://ross.abutalabs.com/products/pulpino
Homepage: http://www.pulp-platform.org
Language: C
License: NOASSERTION
License Family: other
Last push: 2024-02-06T11:08:38+00:00

## Health v2 (maintenance only)
Score: 32/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 3849, "days_push": 939, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1062, forks 325 (observed 2026-08-28T04:03:26.134279+00:00)

## What it is
PULPino is an open-source single-core 32-bit RISC-V microcontroller system developed at ETH Zurich, configurable with either the RISCY or zero-riscy core. It includes a rich set of peripherals (I2C, SPI, I2S, UART), supports RTL simulation, FPGA deployment, and was taped out as an ASIC in 65nm.

## Use cases
- build a RISC-V microcontroller system for embedded projects
- simulate a RISC-V SoC in RTL before FPGA or ASIC implementation
- develop ultra-low-power IoT applications on an open hardware platform
- learn RISC-V architecture and microcontroller design
- run bare-metal C programs on a RISC-V core with JTAG debugging
- evaluate RISCY vs zero-riscy cores for energy-efficient signal processing

## When to choose
- you need an open-source, silicon-proven RISC-V microcontroller platform
- you want to prototype on FPGA or simulate RTL with ModelSim
- you target ultra-low-power or ultra-low-area embedded applications
- you want full debug support and peripheral access (I2C, SPI, UART, I2S)

## When to avoid
- you need multi-core support or µDMA - use PULPissimo instead
- you need a modern, actively developed platform - PULPino is in maintenance mode
- you need a high-performance application processor rather than a microcontroller
- you cannot work with SystemVerilog RTL and simulation toolchains

## Facets
- artifact type: application
- maturity: maintenance
- function: embedded, simulation, developer-tools
- domain: embedded-systems, hardware, autonomous-vehicles
- platform: embedded, cli
- tags: risc-v, microcontroller, systemverilog, fpga, rtl-simulation, ultra-low-power, iot, soc, linux

## Member repositories
- pulp-platform/pulpino (main) score 32

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:26.134279+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:56:46.210039+00:00, confidence not recorded.
  - readme: https://github.com/pulp-platform/pulpino (fetched 2026-08-28T04:03:26.134279+00:00, sha 9a5605feaead)
  - homepage: http://www.pulp-platform.org (fetched 2026-08-29T12:58:30.549771+00:00, sha 3ff8de4ecfd3)
  - site_page: https://pulp-platform.org/faq.html (fetched 2026-08-29T12:58:30.558732+00:00, sha 4221883eceb2)
- Data as of 2026-08-30T08:39:29.467469+00:00.