pulp-platform/axi

Health v2 · maintenance only

Flags: no_license

Adoption not part of the score

1706 stars · 374 forks observed · 2026-09-26

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

A collection of synthesizable SystemVerilog IP modules for building AXI4 and AXI4-Lite on-chip communication networks, including crossbars, multiplexers, converters, and DMA endpoints. It also provides verification infrastructure for testing AXI-based hardware designs.

Use cases

• build an AXI interconnect for an FPGA SoC
• connect IP cores with an AXI4 crossbar
• convert AXI data widths between heterogeneous subnetworks
• verify AXI protocol compliance in simulation
• implement a network-on-chip for an ASIC design
• add DMA engines and memory controllers to an AXI bus

When to choose

• you are designing an FPGA or ASIC with AXI-based on-chip communication
• you need modular, parameterizable AXI building blocks rather than a fixed configuration
• you require full AXI4/AXI4-Lite standard compliance with broad EDA tool support

When to avoid

• you need a software library or driver, not RTL hardware modules
• your project uses a different bus protocol such as Wishbone or APB exclusively
• you cannot use the Solderpad Hardware License (SHL-0.51)

Facets

library · maturity active

simulation embedded hardware embedded-systems axi4 axi4-lite systemverilog rtl network-on-chip interconnect crossbar fpga asic verification

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