# pulp-platform/axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Repository: https://github.com/pulp-platform/axi
Canonical: https://ross.abutalabs.com/products/pulp-platform-axi
Language: SystemVerilog
License: NOASSERTION
License Family: other
Topics: axi, axi4, axi4-lite, systemverilog, hardware, network-on-chip, asic, fpga, rtl, ip
Last push: 2026-08-26T18:37:59+00:00

## Health v2 (maintenance only)
Score: 87/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 65, longevity 100
- inputs: {"age_days": 3065, "days_push": 7, "days_rel": 75, "gap_med": 94.5, "n_releases_24m": 7}
- flags: no_license
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1666, forks 368 (observed 2026-08-28T04:05:18.985133+00:00)

## What it is
A collection of synthesizable SystemVerilog IP modules for building AXI4 and AXI4-Lite on-chip communication networks, including crossbars, multiplexers, converters, and DMA endpoints. It also provides verification infrastructure for testing AXI-based hardware designs.

## Use cases
- build an AXI interconnect for an FPGA SoC
- connect IP cores with an AXI4 crossbar
- convert AXI data widths between heterogeneous subnetworks
- verify AXI protocol compliance in simulation
- implement a network-on-chip for an ASIC design
- add DMA engines and memory controllers to an AXI bus

## When to choose
- you are designing an FPGA or ASIC with AXI-based on-chip communication
- you need modular, parameterizable AXI building blocks rather than a fixed configuration
- you require full AXI4/AXI4-Lite standard compliance with broad EDA tool support

## When to avoid
- you need a software library or driver, not RTL hardware modules
- your project uses a different bus protocol such as Wishbone or APB exclusively
- you cannot use the Solderpad Hardware License (SHL-0.51)

## Facets
- artifact type: library
- maturity: active
- function: simulation, embedded
- domain: hardware, embedded-systems
- platform: -
- tags: axi4, axi4-lite, systemverilog, rtl, network-on-chip, interconnect, crossbar, fpga, asic, verification

## Member repositories
- pulp-platform/axi (main) score 87

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:18.985133+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:43:00.118377+00:00, confidence not recorded.
  - readme: https://github.com/pulp-platform/axi (fetched 2026-08-28T04:05:18.985133+00:00, sha 69de77687359)
- Data as of 2026-08-30T08:39:29.467469+00:00.