YosysHQ/picorv32

Health v2 · maintenance only

Adoption not part of the score

4362 stars · 992 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

PicoRV32 is a size-optimized RISC-V RV32IMC CPU core written in Verilog, configurable as RV32E/I/IC/IM/IMC with optional interrupt controller and co-processor interface. It is designed as an auxiliary processor for FPGA designs and ASICs, occupying only 750-2000 LUTs on Xilinx 7-series FPGAs with high maximum clock frequencies.

Use cases

• add a small auxiliary CPU to an FPGA design
• embed a RISC-V core in an ASIC
• implement a soft CPU with minimal LUT usage
• run bare-metal RISC-V firmware on an FPGA
• integrate a processor without crossing clock domains
• build a custom RV32E embedded controller

When to choose

• you need a very small, configurable RISC-V soft core for FPGA or ASIC
• high fmax and easy timing closure matter more than top performance
• you want a permissively licensed (ISC) CPU core you can extend via the co-processor interface

When to avoid

• you need a high-performance application-class processor with caches and MMU
• you want a fully verified, formally certified CPU for safety-critical products
• you need out-of-order execution or Linux-capable features

Facets

library · maturity stable

embedded simulation hardware embedded-systems risc-v cpu-core fpga asic verilog soft-cpu

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