lowRISC/opentitan

Health v2 · maintenance only

Adoption not part of the score

3607 stars · 1096 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-29, confidence not recorded

OpenTitan is an open-source silicon Root of Trust (RoT) project providing commercial-grade, security-certified hardware IP blocks written in SystemVerilog, along with accompanying firmware, software, and tooling. It is stewarded by lowRISC and ships in production silicon, notably as the hardware security chip in Google Chromebooks.

Use cases

• build a custom silicon root of trust chip
• integrate open-source hardware security IP into an SoC design
• simulate and verify a root of trust design with Verilator or FPGA
• study a production-grade open-source hardware security architecture
• implement secure boot and key management in hardware
• audit hardware root of trust designs for security flaws

When to choose

• you need transparent, auditable, permissively licensed (Apache-2.0) hardware security IP
• you are designing a chip or platform that requires a silicon root of trust
• you want proven IP already validated in high-volume commercial production
• you need a vendor- and platform-agnostic RoT design

When to avoid

• you need a simple software-only security solution without hardware involvement
• you lack SystemVerilog/hardware design expertise and cannot run simulation or FPGA workflows
• you need a small, lightweight library rather than a large monorepo of hardware IP
• your project requires proprietary vendor-specific security features

Facets

framework · maturity stable

security cryptography embedded simulation testing sdk security hardware embedded-systems developer-tools embedded python cpp root-of-trust systemverilog open-source-hardware silicon-ip secure-boot fpga verilator risc-v hardware-security linux docker

Member repositories

For agents

markdown · JSON · MCP: product_card(name="lowRISC/opentitan")