# lowRISC/opentitan

OpenTitan: Open source silicon root of trust

Repository: https://github.com/lowRISC/opentitan
Canonical: https://ross.abutalabs.com/products/opentitan
Homepage: https://www.opentitan.org
Language: SystemVerilog
License: Apache-2.0
License Family: permissive
Last push: 2026-08-26T21:20:38+00:00

## Health v2 (maintenance only)
Score: 83/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 99, release rhythm 54, longevity 100
- inputs: {"age_days": 2564, "days_push": 7, "days_rel": 92, "gap_med": 592, "n_releases_24m": 2}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 3607, forks 1096 (observed 2026-08-28T04:08:11.540496+00:00)

## What it is
OpenTitan is an open-source silicon Root of Trust (RoT) project providing commercial-grade, security-certified hardware IP blocks written in SystemVerilog, along with accompanying firmware, software, and tooling. It is stewarded by lowRISC and ships in production silicon, notably as the hardware security chip in Google Chromebooks.

## Use cases
- build a custom silicon root of trust chip
- integrate open-source hardware security IP into an SoC design
- simulate and verify a root of trust design with Verilator or FPGA
- study a production-grade open-source hardware security architecture
- implement secure boot and key management in hardware
- audit hardware root of trust designs for security flaws

## When to choose
- you need transparent, auditable, permissively licensed (Apache-2.0) hardware security IP
- you are designing a chip or platform that requires a silicon root of trust
- you want proven IP already validated in high-volume commercial production
- you need a vendor- and platform-agnostic RoT design

## When to avoid
- you need a simple software-only security solution without hardware involvement
- you lack SystemVerilog/hardware design expertise and cannot run simulation or FPGA workflows
- you need a small, lightweight library rather than a large monorepo of hardware IP
- your project requires proprietary vendor-specific security features

## Facets
- artifact type: framework
- maturity: stable
- function: security, cryptography, embedded, simulation, testing, sdk
- domain: security, hardware, embedded-systems, developer-tools
- platform: embedded, python, cpp
- tags: root-of-trust, systemverilog, open-source-hardware, silicon-ip, secure-boot, fpga, verilator, risc-v, hardware-security, linux, docker

## Member repositories
- lowRISC/opentitan (main) score 83

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:08:11.540496+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-29T18:33:41.806672+00:00, confidence not recorded.
  - readme: https://github.com/lowRISC/opentitan (fetched 2026-08-28T04:08:11.540496+00:00, sha b2f37e882141)
  - homepage: https://www.opentitan.org (fetched 2026-08-29T09:26:56.856462+00:00, sha a523ce44352c)
  - site_page: https://opentitan.org/quickstart (fetched 2026-08-29T09:26:56.867515+00:00, sha d30a78a20925)
  - site_page: https://opentitan.org/faq (fetched 2026-08-29T09:26:56.865443+00:00, sha 6fecd42d4d76)
  - site_page: https://opentitan.org:443/book (fetched 2026-08-29T09:26:56.869218+00:00, sha 4adf53dac509)
- Data as of 2026-08-30T08:39:29.467469+00:00.