VLSIDA/OpenRAM

Health v2 · maintenance only

Adoption not part of the score

1119 stars · 281 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

OpenRAM is an open-source Python framework that acts as a compiler for static random access memory (SRAM). It generates layouts, netlists, timing and power models, and placement/routing views needed to integrate SRAM macros into ASIC design flows.

Use cases

• generate SRAM macros for an ASIC design
• create GDS layout and netlists for embedded memory
• produce timing and power models for SRAM blocks
• integrate custom memory into open-source or commercial chip design flows
• explore SRAM designs across different CMOS technology nodes
• automate memory compilation for chip tapeouts

When to choose

• you need fabricable or predictive SRAM macros without commercial memory compiler licenses
• you want an open-source, scriptable memory generator for ASIC research or education
• you need SRAM views (layout, netlists, timing, power) for both open and commercial PDK flows

When to avoid

• you need DRAM, flash, or other non-SRAM memory types
• you require a commercial-grade memory compiler with vendor support and guaranteed PDK signoff
• you are not working in chip/VLSI design at all

Facets

framework · maturity active

compiler simulation developer-tools sdk hardware embedded-systems developer-tools python cli sram eda asic-design memory-compiler vlsi gdsii netlist-generation ngspice circuit-design automation linux

Member repositories

For agents

markdown · JSON · MCP: product_card(name="VLSIDA/OpenRAM")