# VLSIDA/OpenRAM

An open-source static random access memory (SRAM) compiler.

Repository: https://github.com/VLSIDA/OpenRAM
Canonical: https://ross.abutalabs.com/products/openram
Homepage: http://www.openram.org
Language: Python
License: BSD-3-Clause
License Family: permissive
Topics: sram, gds, netlists, python, ngspice, netgen, magic
Last push: 2026-08-16T17:01:32+00:00

## Health v2 (maintenance only)
Score: 67/100 (v2, computed 2026-09-02T17:46:02.011165+00:00)
- activity 98, release rhythm 8, longevity 100
- inputs: {"age_days": 3591, "days_push": 17, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: none
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1119, forks 281 (observed 2026-08-28T04:03:39.439351+00:00)

## What it is
OpenRAM is an open-source Python framework that acts as a compiler for static random access memory (SRAM). It generates layouts, netlists, timing and power models, and placement/routing views needed to integrate SRAM macros into ASIC design flows.

## Use cases
- generate SRAM macros for an ASIC design
- create GDS layout and netlists for embedded memory
- produce timing and power models for SRAM blocks
- integrate custom memory into open-source or commercial chip design flows
- explore SRAM designs across different CMOS technology nodes
- automate memory compilation for chip tapeouts

## When to choose
- you need fabricable or predictive SRAM macros without commercial memory compiler licenses
- you want an open-source, scriptable memory generator for ASIC research or education
- you need SRAM views (layout, netlists, timing, power) for both open and commercial PDK flows

## When to avoid
- you need DRAM, flash, or other non-SRAM memory types
- you require a commercial-grade memory compiler with vendor support and guaranteed PDK signoff
- you are not working in chip/VLSI design at all

## Facets
- artifact type: framework
- maturity: active
- function: compiler, simulation, developer-tools, sdk
- domain: hardware, embedded-systems, developer-tools
- platform: python, cli
- tags: sram, eda, asic-design, memory-compiler, vlsi, gdsii, netlist-generation, ngspice, circuit-design, automation, linux

## Member repositories
- VLSIDA/OpenRAM (main) score 67

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:39.439351+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:41:09.615812+00:00, confidence not recorded.
  - readme: https://github.com/VLSIDA/OpenRAM (fetched 2026-08-28T04:03:39.439351+00:00, sha 52cd7c6b4ff8)
  - homepage: http://www.openram.org (fetched 2026-08-29T12:45:14.669536+00:00, sha cf6f494fbaf6)
  - registry_pypi: https://pypi.org/pypi/openram/json (fetched 2026-08-29T12:45:14.673839+00:00, sha 43b44e5ceddd)
- Data as of 2026-08-30T08:39:29.467469+00:00.