The-OpenROAD-Project/OpenLane

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

1915 stars · 442 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

OpenLane is an automated RTL-to-GDSII ASIC implementation flow built on OpenROAD, Yosys, Magic, Netgen, KLayout, and custom Python methodology scripts for design exploration and optimization. It is now in maintenance mode, with only critical bugfixes merged; new designs are directed to its successor LibreLane.

Use cases

• convert verilog rtl to gdsii for asic tapeout
• run automated digital place and route with openroad
• synthesize and implement designs on skywater 130nm pdk
• reproduce google mpw or efabless chipignite shuttle tapeouts
• explore and optimize asic implementation parameters
• run drc and lvs checks with magic and netgen

When to choose

• reproducing older tapeouts from Google MPW or Efabless chipIgnite shuttles
• maintaining legacy designs already built with OpenLane 1.x

When to avoid

• starting a new ASIC design project (use LibreLane instead)
• needing active development, new features, or non-critical bugfixes

Facets

framework · maturity maintenance

compiler build-tool developer-tools simulation workflow-automation hardware embedded-systems developer-tools python cli rtl-to-gdsii asic-design-flow vlsi openroad yosys skywater-pdk chip-design rtl2gds tapeout soc-design automation linux macos docker

Member repositories

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markdown · JSON · MCP: product_card(name="The-OpenROAD-Project/OpenLane")