# The-OpenROAD-Project/OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Repository: https://github.com/The-OpenROAD-Project/OpenLane
Canonical: https://ross.abutalabs.com/products/openlane
Homepage: https://openlane.readthedocs.io/
Language: Python
License: Apache-2.0
License Family: permissive
Topics: asic, 130nm, magic, netgen, yosys, openroad, skywater, openram, vlsi, system-on-chip, soc-design, rtl2gds, foundry, rtl, verilog, klayout, caravel
Last push: 2026-03-25T21:24:26+00:00

## Health v2 (maintenance only)
Score: 66/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 74, release rhythm 35, longevity 100
- inputs: {"age_days": 2235, "days_push": 161, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1915, forks 442 (observed 2026-08-28T04:05:53.651847+00:00)

## What it is
OpenLane is an automated RTL-to-GDSII ASIC implementation flow built on OpenROAD, Yosys, Magic, Netgen, KLayout, and custom Python methodology scripts for design exploration and optimization. It is now in maintenance mode, with only critical bugfixes merged; new designs are directed to its successor LibreLane.

## Use cases
- convert verilog rtl to gdsii for asic tapeout
- run automated digital place and route with openroad
- synthesize and implement designs on skywater 130nm pdk
- reproduce google mpw or efabless chipignite shuttle tapeouts
- explore and optimize asic implementation parameters
- run drc and lvs checks with magic and netgen

## When to choose
- reproducing older tapeouts from Google MPW or Efabless chipIgnite shuttles
- maintaining legacy designs already built with OpenLane 1.x

## When to avoid
- starting a new ASIC design project (use LibreLane instead)
- needing active development, new features, or non-critical bugfixes

## Facets
- artifact type: framework
- maturity: maintenance
- function: compiler, build-tool, developer-tools, simulation, workflow-automation
- domain: hardware, embedded-systems, developer-tools
- platform: python, cli
- tags: rtl-to-gdsii, asic-design-flow, vlsi, openroad, yosys, skywater-pdk, chip-design, rtl2gds, tapeout, soc-design, automation, linux, macos, docker

## Member repositories
- The-OpenROAD-Project/OpenLane (main) score 66

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:05:53.651847+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T03:10:18.766108+00:00, confidence not recorded.
  - readme: https://github.com/The-OpenROAD-Project/OpenLane (fetched 2026-08-28T04:05:53.651847+00:00, sha ad7ba1daca24)
- Data as of 2026-08-30T08:39:29.467469+00:00.