open-logic/open-logic

Health v2 · maintenance only

Flags: no_license no_readme

Adoption not part of the score

1014 stars · 117 forks observed · 2026-09-24

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Open Logic is a VHDL-2008 standard library for FPGA projects, providing reusable, vendor- and tool-independent hardware components under a permissive license. It aims to be the equivalent of stdlib for HDL development and can also be instantiated from SystemVerilog.

Use cases

• reuse common FPGA components across vendor tools
• build VHDL projects with a standard library of building blocks
• use VHDL components from SystemVerilog designs
• develop FPGA firmware for commercial projects with a permissive license
• avoid rewriting common HDL utilities for each project

When to choose

• you develop FPGA designs in VHDL-2008 and want reusable, tool-independent components
• you need a permissively licensed HDL library usable in commercial projects
• you want cross-language usage from SystemVerilog

When to avoid

• your project targets Verilog-only toolchains without VHDL support
• you need components not covered by the library's entity list
• you require an officially standardized library

Facets

library · maturity active

developer-tools embedded embedded-systems hardware developer-tools embedded cross-platform vhdl fpga hdl standard-library system-verilog

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