aolofsson/oh

Health v2 · maintenance only

Flags: no_releases archived

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1436 stars · 304 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

OH! is an open-source library of silicon-proven Verilog hardware building blocks for ASIC and FPGA design, containing over 150 modules such as FIFOs, SPI, GPIO, DMA, interrupt controllers, and a RISC-V implementation. It is written in standard Verilog (2005) and based on design practices validated from 0.35um to 28nm processes.

Use cases

• find reusable Verilog modules for an ASIC design
• get silicon-proven FIFO, SPI, or GPIO blocks for an FPGA project
• build a chip using a reference design flow
• add a DMA engine or interrupt controller to a hardware design
• learn hardware design practices from a real chip library
• simulate and test Verilog modules with provided scripts

When to choose

• you need silicon-validated or FPGA-validated Verilog building blocks
• you are designing an ASIC or FPGA and want proven components instead of writing from scratch
• you want a RISC-V implementation or point-to-point link as a starting point

When to avoid

• you need a high-level hardware description language like Chisel or SystemVerilog with UVM
• you require fully validated versions of modules marked as work-in-progress (hard hat area)
• your project is software-only and unrelated to hardware design

Facets

library · maturity active

embedded sdk developer-tools hardware embedded-systems developer-tools embedded verilog fpga asic hardware-design rtl chip-design silicon-proven risc-v spi dma

Member repositories

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