# aolofsson/oh

Verilog library for ASIC and FPGA designers

Repository: https://github.com/aolofsson/oh
Canonical: https://ross.abutalabs.com/products/oh
Language: Verilog
License: MIT
License Family: permissive
Archived: true
Last push: 2024-05-08T03:14:16+00:00

## Health v2 (maintenance only)
Score: 10/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 0, release rhythm 35, longevity 100
- inputs: {"age_days": 4152, "days_push": 847, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases, archived
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1436, forks 304 (observed 2026-08-28T04:04:43.612469+00:00)

## What it is
OH! is an open-source library of silicon-proven Verilog hardware building blocks for ASIC and FPGA design, containing over 150 modules such as FIFOs, SPI, GPIO, DMA, interrupt controllers, and a RISC-V implementation. It is written in standard Verilog (2005) and based on design practices validated from 0.35um to 28nm processes.

## Use cases
- find reusable Verilog modules for an ASIC design
- get silicon-proven FIFO, SPI, or GPIO blocks for an FPGA project
- build a chip using a reference design flow
- add a DMA engine or interrupt controller to a hardware design
- learn hardware design practices from a real chip library
- simulate and test Verilog modules with provided scripts

## When to choose
- you need silicon-validated or FPGA-validated Verilog building blocks
- you are designing an ASIC or FPGA and want proven components instead of writing from scratch
- you want a RISC-V implementation or point-to-point link as a starting point

## When to avoid
- you need a high-level hardware description language like Chisel or SystemVerilog with UVM
- you require fully validated versions of modules marked as work-in-progress (hard hat area)
- your project is software-only and unrelated to hardware design

## Facets
- artifact type: library
- maturity: active
- function: embedded, sdk, developer-tools
- domain: hardware, embedded-systems, developer-tools
- platform: embedded
- tags: verilog, fpga, asic, hardware-design, rtl, chip-design, silicon-proven, risc-v, spi, dma

## Member repositories
- aolofsson/oh (main) score 10

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:04:43.612469+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T04:36:46.694977+00:00, confidence not recorded.
  - readme: https://github.com/aolofsson/oh (fetched 2026-08-28T04:04:43.612469+00:00, sha 74c46f600529)
- Data as of 2026-08-30T08:39:29.467469+00:00.