myhdl/myhdl

Health v2 · maintenance only

Flags: no_releases

Adoption not part of the score

1126 stars · 252 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

MyHDL is a pure Python package that turns Python into a hardware description and verification language (HDL). Designs written in MyHDL can be simulated, unit-tested with Python tooling, and automatically converted to Verilog or VHDL for standard FPGA/ASIC implementation flows.

Use cases

• model and simulate digital hardware in Python
• write testbenches for hardware designs using pytest
• convert Python hardware designs to Verilog or VHDL
• verify generated Verilog via co-simulation
• design FPGA and ASIC logic with Python tooling
• model counters, flip-flops, and sequential circuits

When to choose

• you want to use Python's ecosystem for hardware design and verification
• you need automatic conversion of high-level designs to Verilog/VHDL
• you prefer Python unit testing frameworks for hardware testbenches
• you want fast simulation via PyPy's JIT

When to avoid

• you need a mature, actively developed HDL with large community support
• you require vendor-specific FPGA primitives and toolchain integration out of the box
• you need a stable PyPI release - the PyPI version lags behind the master branch
• you need system-level verification features of SystemVerilog/UVM

Facets

library · maturity maintenance

simulation testing compiler developer-tools embedded-systems hardware developer-tools python cross-platform hdl hardware-description-language fpga asic verilog vhdl hardware-verification testbenches co-simulation automation

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