# myhdl/myhdl

The MyHDL development repository

Repository: https://github.com/myhdl/myhdl
Canonical: https://ross.abutalabs.com/products/myhdl
Homepage: http://www.myhdl.org
Language: Python
License: LGPL-2.1
License Family: copyleft
Last push: 2025-04-10T18:55:22+00:00

## Health v2 (maintenance only)
Score: 39/100 (v2, computed 2026-09-03T02:20:16.233290+00:00)
- activity 15, release rhythm 35, longevity 100
- inputs: {"age_days": 4225, "days_push": 510, "days_rel": null, "gap_med": null, "n_releases_24m": 0}
- flags: no_releases
- formula: round(0.45*activity + 0.35*rhythm + 0.20*longevity); archived -> min(score, 10)

## Adoption (not part of the score)
Stars 1126, forks 252 (observed 2026-08-28T04:03:41.242843+00:00)

## What it is
MyHDL is a pure Python package that turns Python into a hardware description and verification language (HDL). Designs written in MyHDL can be simulated, unit-tested with Python tooling, and automatically converted to Verilog or VHDL for standard FPGA/ASIC implementation flows.

## Use cases
- model and simulate digital hardware in Python
- write testbenches for hardware designs using pytest
- convert Python hardware designs to Verilog or VHDL
- verify generated Verilog via co-simulation
- design FPGA and ASIC logic with Python tooling
- model counters, flip-flops, and sequential circuits

## When to choose
- you want to use Python's ecosystem for hardware design and verification
- you need automatic conversion of high-level designs to Verilog/VHDL
- you prefer Python unit testing frameworks for hardware testbenches
- you want fast simulation via PyPy's JIT

## When to avoid
- you need a mature, actively developed HDL with large community support
- you require vendor-specific FPGA primitives and toolchain integration out of the box
- you need a stable PyPI release - the PyPI version lags behind the master branch
- you need system-level verification features of SystemVerilog/UVM

## Facets
- artifact type: library
- maturity: maintenance
- function: simulation, testing, compiler, developer-tools
- domain: embedded-systems, hardware, developer-tools
- platform: python, cross-platform
- tags: hdl, hardware-description-language, fpga, asic, verilog, vhdl, hardware-verification, testbenches, co-simulation, automation

## Member repositories
- myhdl/myhdl (main) score 39

## Provenance
- Observed fields: from GitHub, fetched 2026-08-28T04:03:41.242843+00:00.
- Health v2: computed from the inputs above; adoption is never an input.
- Inferred fields (summary, facets, guidance): AI-extracted, prompt v1, taxonomy v1, on 2026-08-30T06:39:12.700196+00:00, confidence not recorded.
  - readme: https://github.com/myhdl/myhdl (fetched 2026-08-28T04:03:41.242843+00:00, sha af60d60717af)
  - homepage: http://www.myhdl.org (fetched 2026-08-29T12:44:01.812671+00:00, sha 7ac53906b847)
  - site_page: https://www.myhdl.org/start/installation.html (fetched 2026-08-29T12:44:01.821473+00:00, sha 01c114ecd220)
  - site_page: https://www.myhdl.org/docs (fetched 2026-08-29T12:44:01.823361+00:00, sha b5c589303b86)
  - site_page: https://www.myhdl.org/docs/examples (fetched 2026-08-29T12:44:01.825067+00:00, sha 6a4a6b5ec65d)
  - site_page: https://www.myhdl.org/docs/performance.html (fetched 2026-08-29T12:44:01.826910+00:00, sha ba1154249ccd)
  - site_page: https://www.myhdl.org/support/faq.html (fetched 2026-08-29T12:44:01.829289+00:00, sha 9479566c5971)
  - site_page: http://dev.myhdl.org (fetched 2026-08-29T12:44:01.831346+00:00, sha 3c02008811f4)
  - site_page: https://www.myhdl.org/news/releases (fetched 2026-08-29T12:44:01.833180+00:00, sha f362944b5ac1)
- Data as of 2026-08-30T08:39:29.467469+00:00.