m-labs/migen

Health v2 · maintenance only

Flags: no_releases archived no_license

Adoption not part of the score

1328 stars · 219 forks observed · 2026-08-28

What it is AI-extracted, prompt v1, taxonomy v1, 2026-08-30, confidence not recorded

Migen is a Python-based toolbox for building complex digital hardware, replacing the event-driven paradigm of Verilog/VHDL with combinatorial and synchronous statements while allowing logic to be generated by Python programs. It includes libraries for system-on-chip interconnect, dataflow programming, high-level synthesis, and Python-based simulation.

Use cases

• generate FPGA logic with Python instead of Verilog
• build a system-on-chip design programmatically
• write hardware test benches in Python
• synthesize Python routines into state machines with datapaths
• create reusable, parameterized hardware designs via metaprogramming
• design ASIC or FPGA circuits with sane integer arithmetic

When to choose

• you want to leverage Python's expressiveness for hardware design
• you are building synchronous digital circuits and find Verilog/VHDL tedious
• you need procedural generation of logic beyond HDL generate statements
• you are working on MiSoC or ARTIQ-related hardware

When to avoid

• you need an industry-standard HDL flow with existing Verilog/VHDL toolchain integration
• your design is primarily asynchronous or event-driven
• you need a large community and ecosystem like Chisel or SystemVerilog
• you require commercial vendor support

Facets

library · maturity maintenance

compiler simulation developer-tools hardware embedded-systems python cross-platform hdl fpga asic hardware-design fhdl misoc metaprogramming automation

Member repositories

For agents

markdown · JSON · MCP: product_card(name="m-labs/migen")